sti5202 cannot get box ON

JTAG on Dish Receivers.
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jekkos
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Posts: 14
Joined: Wed Apr 04, 2012 5:15 am

sti5202 cannot get box ON

Post by jekkos »

Currently Im trying to connect to a sti5202
output is the following

-detect
IDCODE 2D42C041
STi STi5202
========================================
DeviceId = 0x2D42C041
OptionId = 0x00D3878D
PrivateId = 0x00E10822
ExtraId = 0x84D558F1
========================================
HUDI Internal Status
----------------------------------------
SR = 0xFFFFFFFF
FPSCR = 0xFFFFFFFF
CCR = 0x7F
FRQCR = 0x0FFF
EXPEVT = 0x0FFF
INTEVT = 0x3FFC
EBUS = 0x1FFFFFFF
IBUS = 0xFFFFFFFF
SBUS = 0xFFFFFFFF
EBTYPE = 0x7F
SBTYPE = 0x0F
CMF = 0x3F
SCMF = 0x0F
MMUCRAT = 0x01
PTEH = 0xFF
STATUS = 0x03
currently I can't get BOX ON. I used the B600V4 as a template. The device has four Hynix HY5DU121622DTP-D43 RAM chips (64Mbit each?)
the Flash chip has a sticker on it, will post pic here

Image

probably will need to adapt the ram configuration here as well? Can anyone see something wrong in the internal register statuses?

thanks
usbbdm
Junior Member
Posts: 8962
Joined: Mon Jul 18, 2005 9:33 pm

Post by usbbdm »

How do you connect the JTAG?
usbbdm
Junior Member
Posts: 8962
Joined: Mon Jul 18, 2005 9:33 pm

Post by usbbdm »

You need to connect reset pin as well as the TRST on pin 13 (not pin1).

http://www.usbjtag.com/jtagnt/ird/sv8000.php
jekkos
Junior Member
Posts: 14
Joined: Wed Apr 04, 2012 5:15 am

Post by jekkos »

I connected pin 13 to trst.
I connected nrst to pin 11 on usbjtagnt
When I do the later then the box resets when clicking detect. Maybe this pin is active low?
I found similar thread here reporting this issue (reset on detect).
was there a solution to this after all (extra reset circuitry eg)

thanks.
usbbdm
Junior Member
Posts: 8962
Joined: Mon Jul 18, 2005 9:33 pm

Post by usbbdm »

jekkos wrote:I connected pin 13 to trst.
I connected nrst to pin 11 on usbjtagnt
When I do the later then the box resets when clicking detect. Maybe this pin is active low?
I found similar thread here reporting this issue (reset on detect).
was there a solution to this after all (extra reset circuitry eg)

thanks.
You are getting closer. When box is in TRAP ON mode, it does stop the target.
Detect is triggering by the reset pin and TRST in special order. What is the result on the display?
jekkos
Junior Member
Posts: 14
Joined: Wed Apr 04, 2012 5:15 am

Post by jekkos »

usbbdm wrote:You are getting closer. When box is in TRAP ON mode, it does stop the target.
Detect is triggering by the reset pin and TRST in special order. What is the result on the display?
ok I tried another time, box is resetting but not getting any box on or trap on. The dialog still says box off.

I suppose the code you used is based on the urjtag patch. I applied it and get similar output there. I can load in the overlay in aseram but seems to be a problem with an ASEBRK assert.

I suppose I need peek/poke from the overlay first to be able to query the flash. Now I see
flshdct 0
Unknown flash type!
Report these values http://www.usbjtag.com/vbforum ffff,ffff
IDCODE 2D42C041
STi STi5202
========================================
DeviceId = 0x2D42C041
OptionId = 0x00D3878D
PrivateId = 0x01000822
ExtraId = 0x00000000
========================================
HUDI Internal Status
----------------------------------------
SR = 0xFFFFFFFF
FPSCR = 0xFFFFFFFF
CCR = 0x7F
FRQCR = 0x0FFF
EXPEVT = 0x0FFF
INTEVT = 0x3FFC
EBUS = 0x1FFFFFFF
IBUS = 0x01FFFFFF
SBUS = 0xFFFFFFFF
EBTYPE = 0x7F
SBTYPE = 0x0F
CMF = 0x3F
SCMF = 0x0F
MMUCRAT = 0x01
PTEH = 0xFF
STATUS = 0x03
usbbdm
Junior Member
Posts: 8962
Joined: Mon Jul 18, 2005 9:33 pm

Post by usbbdm »

HUDI Internal Status
are all FFs. That is not good sign.
jekkos
Junior Member
Posts: 14
Joined: Wed Apr 04, 2012 5:15 am

Post by jekkos »

usbbdm wrote:HUDI Internal Status
are all FFs. That is not good sign.
Ok I found some technical details on sti5202
/*
* Base addresses for control register banks.
*
* Define STI5202_MOVE_LMI_REGS to 0 in order to keep the LMI configuration
* registers at their reset addresses (by default the connection scripts and
* bootstrap memory initialisations will move these registers to their area 6
* addresses).
*/

/* Area 6 on-chip peripherals base */
#ifndef STI5202_AREA6_PERIPH_BASE
#define STI5202_AREA6_PERIPH_BASE 0xb8000000
#endif

#ifndef STI5202_MOVE_LMI_REGS
#define STI5202_MOVE_LMI_REGS 1
#endif

/* Generic SH4 control registers */
#ifndef SH4_TMU_REGS_BASE
#define SH4_TMU_REGS_BASE 0xffd80000
#endif
#ifndef SH4_RTC_REGS_BASE
#define SH4_RTC_REGS_BASE 0xffc80000
#endif

/* Common ST40 control registers */
#ifndef ST40_CPG_REGS_BASE
#define ST40_CPG_REGS_BASE 0xffc00000
#endif
#ifndef ST40_INTC_REGS_BASE
#define ST40_INTC_REGS_BASE 0xffd00000
#endif
#ifndef ST40_SCIF2_REGS_BASE
#define ST40_SCIF2_REGS_BASE 0xffe80000
#endif

#ifndef ST40_ILC_REGS_BASE
#define ST40_ILC_REGS_BASE STI5202_AREA6_PERIPH_BASE
#endif
#ifndef ST40_INTC2_REGS_BASE
#define ST40_INTC2_REGS_BASE (STI5202_AREA6_PERIPH_BASE + 0x01001300)
#endif
any idea what variable I should use in the config file? program ram.. there is no documentation on these xml files. Also code is not opensource so I can't figure out myself

<ST40Ver>2</ST40Ver>
<Programram>0x84000000</Programram>
<NANDData>st7105nand.dat</NANDData>

What does st40Ver mean?
Also program ram is is the same as ASERAM address?
NandData, is a binary file, how is it used?
jekkos
Junior Member
Posts: 14
Joined: Wed Apr 04, 2012 5:15 am

Post by jekkos »

I found the following in st40 toolset

## Reset STb7100 leaving ST40 in reset hold
jtag ntrst=0
_jtagSleep $STb7100ResetDelay
jtag nrst=0
_jtagSleep $STb7100ResetDelay
jtag asebrk=0
_jtagSleep $STb7100ResetDelay
jtag nrst=1
_jtagSleep $STb7100ResetDelay
jtag asebrk=1
_jtagSleep $STb7100ResetDelay
jtag ntrst=1
seems that to boot correctly one needs to toggle ASEBRK (emulation enable) pin as well. Is this the same as the RST pin indicated on the connection diagram or is this another?
usbbdm
Junior Member
Posts: 8962
Joined: Mon Jul 18, 2005 9:33 pm

Post by usbbdm »

You should try to select different st40 target. Notice St40Ver? There is V1 and V2.
Check the IPTV target and see if you get any luck.
Also please play with the power on and detect timing. With different timing you might get TRAP ON. But try different target as well. If your target does not use NAND device you should not select this target.
jekkos
Junior Member
Posts: 14
Joined: Wed Apr 04, 2012 5:15 am

Post by jekkos »

usbbdm wrote:You should try to select different st40 target. Notice St40Ver? There is V1 and V2.
Check the IPTV target and see if you get any luck.
Also please play with the power on and detect timing. With different timing you might get TRAP ON. But try different target as well. If your target does not use NAND device you should not select this target.
Think it uses a nand bga chip (visible in the picture above here). I was looking into st40 toolset found plenty of gdb scripts to initialize jtag chain.

Also I wonder if no specific setup is needed for sdram bus. In most files I see some init pokes specific for the box. Any idea if this might need to be adapted? Is there another sti5202 cpu present in one of the config files?
usbbdm
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Posts: 8962
Joined: Mon Jul 18, 2005 9:33 pm

Post by usbbdm »

The init will only work when going to TRAP ON. go too tools and config select ST40 you will see all the ST40 targets. Nand or not is not important now. Entering TRAP ON is most important.
jekkos
Junior Member
Posts: 14
Joined: Wed Apr 04, 2012 5:15 am

Post by jekkos »

usbbdm wrote:The init will only work when going to TRAP ON. go too tools and config select ST40 you will see all the ST40 targets. Nand or not is not important now. Entering TRAP ON is most important.
ok I understand.. init will need poke functionality.. in this case only available when trap is on. USBJTag needs to upload piece of assembly into memory? then force the cpu to execute these loaded functions (peek/poke) this is what is called TRAP ON.

Of course you will first need DEBUG ON and this does require memory address to load peek/poke assembly? I thought that would be reason to toggle ASEBRK pin, as it will enable emulation mode so we can control cpu (DEBUG ON) and load st functions into ram. Or maybe this is the same as RST pin as indicated in the connection schematics.
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